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JSSC 2020第10期Memory55nmSRAMNeural Network Accelerator

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro fo

提出一种1至8位可配置的6T SRAM存内计算单元宏，提升读取精度和能效。
55nm CMOS, 3.5ns每周期, 0.6–40.2 TOPS/W
存内计算6T SRAM可配置能效读取精度
▸混合结构结合6T-SRAM存内二进制乘积和操作与数字近存计算多比特乘积和累加
▸基于列的位值分组权重映射和串行位输入映射方案
▸自参考多级读取器和输入感知位线电压补偿方案
Abstract
Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high- precision operations, large cell array area overhead, and limited compatibility with many input and weight configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing multibit PS accumulation to increase read accuracy and reduce area overhead; 2) column-