A 65-125-Gbs Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Abstract

This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally con- trolled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby impr ove the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly