← 返回 JSSC 论文列表JSSC 2020第10期Data Converters180nmSAR ADC
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Havin
一种基于CDAC的单电源缓冲嵌入式SAR ADC，采用跳复位方案，具有高能效和轨到轨信号摆幅。
180nm CMOS, 640-kHz BW, 74.8-dB SNDR, 89.1-dB SFDR, 180.1 μW
SAR ADC单电源缓冲嵌入式跳复位方案电容电平移位
▸创新点1：电容电平移位偏置方案实现轨到轨信号摆幅（电路创新）。该方案通过电容耦合实现电平移位，使得源极跟随器缓冲器在单电源供电下仍能支持全摆幅输入信号，显著提升了动态范围，适用于低电压设计。
▸创新点2：负升压电路解决偏置泄漏问题（电路创新）。提出的负升压电路采用薄氧晶体管设计，通过开关电容技术消除偏置泄漏，同时避免了器件可靠性问题，为电平移位提供了稳定的负偏置电压。
▸创新点3：跳复位方案降低功耗（系统创新）。结合8倍过采样和低功耗增量读出方法，该方案通过跳过冗余复位操作减少功耗，并具备固有斩波功能，实测功耗仅180.1μW，Schreier FoM达167.3dB。
▸创新点4：缓冲器嵌入SAR ADC架构（系统创新）。将源极跟随器缓冲器直接集成到SAR ADC的CDAC结构中，优化了信号路径，在0.192mm²面积下实现74.8dB SNDR和89.1dB SFDR，适用于生物医疗等低功耗场景。
Abstract
This article presents a power-efficient buffer-
embedding successive approximation register (SAR) analog-to-
digital converter (ADC) that utilizes a core power supply for
the source-follower buffer, having a rail-to-rail signal swing due
to the capacitive-level shifting bias scheme. Also, to implement
the switched-capacitor (SC) level-shifting bias scheme without
bias leakage issue, a negative boosting circuit is proposed.
The boosting circuit is designed without any reliability issue,
even with