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JSSC 2020第10期Clocking & PLLs180nmNeural Network Accelerator

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator

结合一阶单比特连续时间调制器和二阶MASH后端,实现高稳定性和低噪声的音频调制器。
180-nm CMOS, 100.9-dB SNDR, 24-kHz带宽, 265μW功耗
连续时间调制器FIR反馈MASH ADC时钟抖动噪声传递函数
使用FIR反馈降低时钟抖动敏感性
提高线性度和减少斩波伪影
在MASH ADC中过滤第一级误差波形
Abstract
We combine a first-order single-bit CT M employing finite impulse-response (FIR) feedback with a 1-bit second-order  back end to achieve a modulator with max- imum stable amplitude (MSA) that is close to full scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input stage to reduce clock-jitter sensitivity, improve linearity, and reduce chopping artifacts. We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage. We apply the principle to an audio continuous-time delta–sigma modulator. A prototype chip, fabricated in 180-nm CMOS to demonstrate the principle, achieves 100.9-dB SNDR in a 24-kHz bandwidth and dissipates 265μW. The resulting Schreier figure of merit is 180.5 dB.