← 返回 JSSC 论文列表JSSC 2020第10期Power Management0.35µmNeural Network Accelerator
Stacking Isolated SC Cores for High-V oltage Wide Input Range Monolithic DC–DC Conversion
提出一种堆叠隔离SC核心的全集成DC-DC转换器，支持7.5至42V宽输入范围。
0.35µm CMOS, 3V输出, <5%纹波, 2.1mW峰值功率
DC-DC转换器隔离SC核心宽输入范围电平转换器体偏置电路
▸创新点1：堆叠隔离SC核心实现宽输入范围（系统创新）。通过堆叠多个隔离的开关电容核心，实现了7.5V至42V的宽输入电压范围，解决了传统单核心设计无法覆盖高压差的问题。
▸创新点2：多电压转换比通过核心重构实现（方法创新）。通过动态重构堆叠核心的拓扑结构，实现了多种电压转换比（VCRs），提升了转换器的灵活性和效率。
▸创新点3：集成电平转换器和体偏置电路（电路创新）。设计了高压接口电平转换器和体偏置电路，确保低压核心在高输入电压下稳定工作，峰值输出功率达2.1mW且电压纹波小于5%。
▸创新点4：采用0.35µm CMOS工艺实现全集成（工艺创新）。在低成本标准CMOS工艺上实现了高压DC-DC转换器的全集成，避免了特殊工艺需求，降低了制造成本。
Abstract
A fully integrated DC–DC converter that uses iso- lated switched-capacitor (SC) cores in a stacked way is presented. The converter can transform a wide input voltage range from 7.5 up to 42 V by the multiple available voltage conversion ratios (VCRs), which are realized through reconfiguration of the stackable cores. In addition, stacking simplifies the design to the low-voltage isolated SC core. Level shifters are included to fulfill the high-voltage interfaces, while bulk biasing circuits ensure the correct driving of the switches in the cores. As such, the power converter is implemented in a 0.35- µm CMOS technology and produces a stable 3-V output with less than 5% voltage ripple for a peak output power of 2.1 mW.