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JSSC 2020第11期Data Converters110-nm CMOSDACNeural Network Accelerator

A6 . 5 -μW 10-kHz BW 80.4-dB SNDR G m-C-Based CT  Modulator With a Feedback-Assisted Gm Linearization for Artifact-Tolerant

提出一种基于Gm-C的连续时间ΔΣ调制器,用于抗伪影神经记录接口,具有高线性度和低功耗。
65-μW功耗, 10-kHz带宽, 80.4-dB SNDR, 81-dB动态范围, 76-dB CMRR
Gm-C调制器神经记录线性化技术低功耗连续时间ΔΣ调制器
反馈辅助Gm线性化技术
使用VCO作为第二积分器和相位量化器
在第一积分器采用比例积分传输函数
Abstract
This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted G m lin- earization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input G m.T h i s enables the input G m to process the quantization noise, thereby improving the input range and linearity of the G m-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional– integral (PI) transfer function is employed at the first integra- tor, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mV pp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 µW with a signal band- width of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment. Manuscript received April 27, 2020; revised July 12, 2020; accepted August 10, 2020. This article was approved by Associate Editor Pedram Mohseni. This work was supported in part by the Samsung Re