A 7-bit 900-MSs 2-Then-3-bitcycle SAR ADC With Background Offset Calibration

Abstract

This article presents a 7-bit 900-MS/s multi-bit/cycle successive approximation register (SAR) analog-to-digital con- verter (ADC) with background offset calibration. Unlike prior works that adopt either four capacitive DACs (CDACs) or inter- polated resistive DAC to enable 3-bit/cycle operation, the pro- posed technique uses only two CDACs to realize the same functionality. The number of CDACs is reduced by embedding gain inside the two-path comparators, resulting in reduced power , area, and i