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III-B Digital System Design
设计了一种采用6T SRAM校准的像素电路，以解决质子撞击导致的误触发问题。
8µm×8µm像素尺寸，10-bit量化，6µs LSB采样时间
像素校准6T SRAM质子撞击寄生电容差分放大器
▸采用1-bit 6T SRAM块校准误触发像素
▸优化节点时间常数和寄生电容比例以减少质子撞击影响
▸通过差分放大器和HPF设计抑制误触发信号
Abstract
coming from other pixels. Therefore, an in-pixel standard 1-bit
6T SRAM block is implemented to disable any false-positive
pixel. Disabling these problematic pixels is called calibration
and will be explained in Section III-D.
The overall pixel size is 8µm× 8µm, leading to a fill-
factor of 1/64. This means that there exists a high chance
of protons striking the transistors. Assuming the PN junctions
of the transistors have a similar depletion depth to that of
the diode, this will create a voltag