Abstract
×2, 4, 8, 32 0 .5µs 0 .2µs 32 µs
tP ISO tmst×1, 2, 4, 8 0 .5µs 0 .1µs 8 µs
tSRAM tmst×1, 8, 32, 64 1 µs 0 .1µs 64 µs
them and buffering, and configuring internal parameters. The
SRAM control block manages the enabling and disabling of
pixels, as well as the reading of current SRAM values.
The DL and AL lines on each row have pull-down and pull-
up transistors, respectively. The 10-bit counter starts counting
at the rising edge of the DL signal. During counting, the
addressing block stores the cur