A 12-b 18-GSs RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifi

Abstract

We discuss a 12-b 18-GS/s analog-to-digital con- verter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold ampli- fier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving sampling time and bandwidth mismatch. Above 10 GS/s, the THA is programmed to use two pi