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A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/ μs Slope and 1.2-GHz Chirp-Bandwidth
一款基于积分DAC的12mW 10GHz FMCW PLL，用于雷达应用，具有28kHz RMS频率误差。
28kHz rms-frequency-error, 11.7mW功耗(其中QDAC<0.5mW), 1.21GHz啁啾带宽, 23.6MHz/µs啁啾斜率
FMCW雷达锁相环积分DAC两点调制背景校准
▸采用积分型数模转换器(QDAC)调谐VCO
▸两点调制架构实现宽带低噪声频率调制
▸全背景校准引擎校正QDAC路径非线性
Abstract
A 10-GHz sub-sampling phase-locked loop (PLL) (SSPLL) with wideband low-noise frequency modulation for frequency-modulated continuous-wave (FMCW) radar appli- cations is presented. It uses a low-power charge-integrating digital-to-analog converter (QDAC) to tune the voltage-controlled oscillator (VCO) in a two-point modulation architecture. A full background calibration engine corrects for the nonlinearities in the QDAC modulation path. Implemented in a 28-nm CMOS process, the SSPLL consumes 11.7 mW (of which less-than 0.5 mW from the QDAC) to generate a 23.6-MHz/ µss a w - tooth chirp-slope with 28-kHz rms-frequency-error for 1.21-GHz chirp-bandwidth.