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A 66-fs-rms Jitter 128-to-152-GHz Fractional-N BangBang PLL With Digital Frequen
提出一种低抖动、低杂散的分数N型BangBang锁相环，采用数字频率误差恢复技术实现快速锁定。
28nm CMOS, 0.17mm²核心面积, 66.20fs rms抖动, 19.8mW功耗
分数N锁相环BangBang PLL数字频率误差恢复数字时间转换器低抖动
▸数字频率误差恢复技术实现快速锁定
▸降低静态和动态非线性的数字时间转换器设计
▸低抖动和低杂散的分数N型操作
Abstract
This article presents a fractional- N frequency
synthesizer architecture that is able to overcome the limitations of
conventional bang–bang phase-locked loops. A digital frequency-
error recovery technique is introduced to enable fast lock, at no
significant power or circuit overhead. A digital-to-time converter
design with reduced static and dynamic nonlinearity is proposed,
which allows for low-jitter and low-spur fractional- N operation.
The phase-locked loop (PLL), implemented in a standard 2