A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional- N Bang–Bang PLL With Digital Frequency-Error Recovery for

Abstract

This article presents a fractional- N frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops. A digital frequency- error recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional- N operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm 2. It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 µs. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional- N and integer-N modes, respectively. The worst-case in-band fractional spur is at −61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of −250.6 dB for the fractional- N channels.