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A Cascaded Noise-Shap ing SAR Architecture for Robust
提出级联噪声整形SAR架构，提升系统阶数和信噪比，实现高效稳健的模数转换。
28nm CMOS, 120µW功耗, 0.02mm²面积, 88dB SNDR(100kHz带宽), 177dB Schreier FoM
噪声整形SAR ADC级联架构高信噪比CMOS
▸级联噪声整形(CaNS)SAR架构
▸两相稳定技术提升残差放大效率
▸系统级高阶噪声整形鲁棒性增强
Abstract
The emerging noise-shaping (NS) successive approx- imation (SAR) architecture is highly efficient and compact; how- ever, the order and signal-to-noise ratio (SNR) of sub-MHz NS SAR ADCs are still lower than conventional sigma–delta ADCs. This work proposes a cascaded NS (CaNS) SAR architecture that increases system order and enables more effective NS for higher SNR. The proposed architecture enhances the robustness of high-order NS performance at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the efficiency of residue amplification without sacrificing robustness. A prototype CaNS SAR ADC, fabricated in 28-nm CMOS, occupies 0.02 mm 2 and consumes 120 µW. The measured Signal to Noise and Distortion Ratio (SNDR) over 100-kHz bandwidth is 88 dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB.