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Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gm-Boosting
本文提出了一种E波段低噪声放大器与多馈天线协同设计的方法,通过天线级噪声消除和gm提升技术,实现了高性能无线前端设计。
4.8-dB NF, 2.2-dBm IIP3
E波段低噪声放大器多馈天线噪声消除毫米波
▸创新点1:天线与LNA协同设计(系统创新):通过将多馈天线与低噪声放大器(LNA)直接集成在芯片上,实现了天线与电子元件的协同设计,突破了传统设计中天线仅作为50欧姆辐射负载的限制,显著提升了无线前端性能。
▸创新点2:多馈天线作为被动辐射网络(方法创新):利用多馈天线的被动辐射网络特性,直接在天线层面进行信号处理和调节,增强了信号处理能力,为前端设计提供了新的创新方向。
▸创新点3:天线级噪声消除技术(电路创新):通过共同栅极(CG)和共同源极(CS)LNA路径与近场耦合折叠槽天线的相互作用,实现了天线级的噪声消除,降低了噪声系数(NF),测量结果显示NF低至4.8 dB。
▸创新点4:gm提升技术(电路创新):利用多馈天线与LNA的协同设计,提升了跨导(gm),进一步优化了放大器的性能,实现了2.2 dBm的输入三阶交调点(IIP3),达到了同类频率下的最佳性能指标。
Abstract
This article presents an E-band low-noise ampli- fier (LNA) co-designed and co-integrated with an on-chip multi- feed antenna for antenna-level LNA noise-canceling and g m -boosting. Different from conventional approaches that view antennas as a simple 50- radiation load, we exploit anten- nas as multi-feed passive radiating networks with direct on- antenna signal conditioning and processing capabilities. Such an antenna-electronics co-design concept can potentially advance wireless front-end performance beyond electronics-only designs and opens the door to a plethora of front-end innovations. We also propose equivalent circuits to model multi-feed antenna systems and elucidate on-antenna signal processing operations. As a proof of concept, we propose an antenna-LNA co-designed architecture and explore the interactions among a common-gate (CG) LNA path, a common-source (CS) LNA path, and a pair of near-field coupled folded slot antennas for on-antenna noise-cancellation and g m-boosting. In the measurements, a true Y-factor radiation method is introduced as a new approach to measure the noise figure (NF) of the on-chip multi-feed antenna and LNA/RX integration. Then, we perform the conventional sensitivity-based NF measurement. Both measurements show accurate and consis- tent NF characterization at high millimeter-wave (mm-Wave). The E-band antenna-LNA front end is implemented in the Globalfoundries 45-nm CMOS SOI process and demonstrates 4.8-dB NF with 2.2-dBm IIP 3, achievin