JSSC 2021第1期RF & Wireless7nmHigh-Speed LinkPAM-4

A 112-Gbs PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved

7nm FinFET CMOS工艺下实现的112Gb/s PAM-4长距离有线收发器

112Gb/s PAM-4, <1E-8 PRBS-31 BER, 37.5dB损耗@28GHz, 602mW/通道

PAM-4时间交织ADCFinFET CMOS长距离有线通信电感峰值网络

▸36路时间交织56GS/s 7位ADC

▸基于反相器的Gm/逆Gm负载单元

▸分布式电感峰值网络与多相位时钟校准

Abstract

A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based Gm/inverse- Gm-load cells. A distributed inductor peaking network and multi-phase clock calibration is implemented in the quarter-rate transmitter. The transceiver achieves <1E-8 pseudorandom binary sequence (PRBS)-31 PAM-4 bit error rate