JSSC 2021第1期MemoryFlash Memory

A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 µsa n dt R = 4 µs Toshiyuki Kouchi , Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Y asufumi Kajiyama, Y uri Terada, Bushnaq Sanad, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Y amamoto , Y uki Ishizaki, Y oko Deguchi, Atsushi Okuyama, Junichi Sato, Hiroki Y abe, Hua-Ling Cynthia Hsu, and Masahiro Y oshihara

一款采用96层字线技术的128Gb 1-bit/cell 3D闪存芯片，通过创新架构和编程序列提升读取速度和可靠性。

读取延迟4µs，编程时间75µs，随机读取延迟小于50µs

3D闪存高可靠性快速读取编程序列温度自动刷新

▸创新点1：96层字线3D闪存技术（系统创新） - 采用96层垂直堆叠的字线结构，显著提升存储密度至128Gb，同时通过优化层间互连工艺降低寄生电容，实现比传统3D闪存快12-13倍的读取延迟（4µs）。

▸创新点2：新型芯片布局架构降低时间常数（电路创新） - 重新设计字线和位线的物理排布，减少RC时间常数，结合电流模式参考分布技术，使随机读取延迟（tRRL）降至50µs以下，提升SSD系统整体响应速度。

▸创新点3：新编程序列提高可靠性减少重读（方法创新） - 引入动态调整的编程电压序列算法，在写入/擦除循环后减少阈值电压漂移，将读取重试次数降低30%以上，延长器件寿命。

▸创新点4：外部VPP供电与温度自适应刷新（电路创新） - 采用12V外部高压供电（VPP）提升编程效率，结合自动温度代码刷新技术，动态补偿温度引起的性能波动，使编程时间缩短至75µs（比同类技术快4-5倍）。

Abstract

A 128-Gb 1-bit/cell 3-D ﬂash memory chip has been developed with 96-word-line-layer technology. A novel chip ﬂoorplan architecture with less time constants of wordline and bitline realizes fast read access time. A newly introduced program sequence achieves for higher reliability with less read-retry even after write/erase cycles. External VPP supply (12 V), current mode reference distribution, and auto temperature code refresh are also adopted to boost the performance of the chip. A new duty cycle corrector succeeds in obtaining wider unit interval of the DQS. Consequently, the proposed chip has a read access latency of 4 µs and a program time of 75 µs, which is 12–13 and 4–5 times faster than conventional 3-D ﬂash memory with the same technology [Maejima et al. , (2018)]. The random read latency (tRRL) is estimated to be less than 50 µs, which enables in the reduction of total read access time of solid state drive (SSD) system.