← 返回 JSSC 论文列表JSSC 2021第1期RF & Wireless65nmNeural Network Accelerator
A 22-Gbs Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating
一种采用两比特积分前端的新型22Gb/s低功耗光接收器架构
22Gb/s, BER<10^-12, 1.43pJ/bit
光接收器低功耗时间交织CMOS时钟恢复
▸采用两比特积分低带宽前端替代传统跨阻放大器
▸仅使用两个四分之一速率时钟相位实现1:4解复用
▸通过光学延迟线和分路器简化时钟系统
Abstract
This article presents the implementation of a
novel 22-Gb/s energy-efficient optoelectronic receiver architecture
in 65-nm CMOS for short-reach optical communication. The
receiver incorporates four sub receivers with a two-bit integrating
resettable front-end in each sub receiver. The inputs to two of
the four sub receivers are optically delayed by one bit and two
complementary quarter-rate clock phases are used to completely
recover the data. The two-bit integrating low-bandwidth front
end repla