JSSC 2021第1期Memory5nmSRAM

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal

采用5纳米FinFET技术实现135Mb高密度SRAM，通过创新写入辅助技术降低供电电压。

135Mb容量，0.021µm² 6-T SRAM单元，供电电压降低300mV

SRAMFinFET写入辅助技术高密度存储5纳米工艺

▸金属电容器耦合负位线(NBL)技术

▸电荷共享降低单元VDD(CS-LCV)写入辅助技术

▸飞行位线(FBL)架构提高存储密度

Abstract

A 135-Mb 0.021- µm2 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Si