← 返回 JSSC 论文列表JSSC 2021第1期Power Management65nmBuck Converter
EM and Power SCA-Resilient AES-256 Through 350 Current-Domain Signature Attenuat
通过电流域签名衰减技术提升AES-256的抗侧信道攻击能力
65nm CMOS, 50MHz时钟频率, MTD提升2个数量级
侧信道攻击AES-256电流域衰减电磁分析功耗分析
▸创新点1：电流域签名衰减技术(CDSA) - 该方法创新性地在电流域中实现签名衰减，显著抑制了加密电流中的关键相关信息，从而大幅提升了抗功耗和电磁侧信道分析的能力，MTD提升至2倍。
▸创新点2：局部低层金属布线抑制电磁泄漏 - 该电路创新通过将CDSA嵌入加密IP并使用低层金属布线，有效防止了电磁泄漏，显著降低了高金属层的辐射效应。
▸创新点3：白盒模型指导设计 - 该设计方法首次采用白盒模型深入分析，指导CDSA和局部低层金属布线的实现，确保了设计的高效性和安全性。
▸创新点4：测试向量泄漏评估(TVLA)验证 - 该系统创新首次通过片上测量进行TVLA验证，证明了高金属层的泄漏显著降低，进一步验证了设计的有效性。
Abstract
Mathematically secure cryptographic algorithms,
when implemented on a physical substrate, leak critical
“side-channel” information, leading to power and electromag-
netic (EM) analysis attacks. Circuit-level protections involve
switched capacitor, buck converter, or series low-dropout (LDO)
regulator-based implementations, each of which suffers from
significant power, area, or performance tradeoffs and has only
achieved a minimum traces to disclosure (MTD) of 10 M till date.
Utilizing an in-depth