STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin–Spin Interactions

Abstract

This article presents a high-performance annealing processor named STochAsTIc Cellular automata Annealer (STATICA) for solving combinatorial optimization problems rep- resented by fully connected graphs. Supporting fully connected graphs is strongly required for dealing with realistic optimiza- tion problems. Unlike previous annealing processors that follow Glauber dynamics, our proposed annealer can update multiple states of fully connected spins simultaneously by introducing different dynamics called stochastic cellular automata annealing. It allows us to utilize the pipeline-level and memory-bank-level parallelization in addition to the PE-level parallelization origi- nally adopted in the previous annealers. The STATICA prototype chip, which supports 512-spin fully connected graph, has been fabricated with the 65-nm CMOS technology and realized as a 3m m × 4 mm chip. Using the fabricated 512-spin chip and numerical projections for a 2048-spin chip, we have co nducted experiments to reveal the annealing performance of STATICA and examined how to control its annealing process efficiently.