JSSC 2021第2期Data Converters65nm

A 4-GSs 113-mW 7-bit Time-Based ADC With Folding V oltage-to-Time Converter and

提出一种低功耗折叠电压-时间转换器，用于高速7位时间型ADC。

1V 65nm CMOS, 4GS/s, 11.3mW, 34.58dB SNDR, 64.5fJ/conv.-step

电压-时间转换器时间型ADC低功耗折叠技术高速

▸创新点1：折叠电压-时间转换器（Folding VTC）方法创新，通过多次折叠输入电压范围，将非线性问题分解为多个线性区间，显著提升转换线性度（SNDR达34.58dB）

▸创新点2：单时间输出架构电路创新，与传统多输出VTC相比，减少TDC比较器数量，降低功耗至113mW，同时保持7-bit分辨率

▸创新点3：混合型量化系统创新，结合2-bit折叠VTC数字输出与5-bit流水线TDC，在4GS/s高速下实现64.5fJ/conv.-step的超低FoM

▸创新点4：1V 65nm CMOS工艺优化，通过折叠结构压缩电压摆幅，使低压设计兼容高线性度（转换增益提升3倍）

Abstract

A folding voltage-to-time converter (VTC) is pro- posed for low-power time-based (TB) ﬂash ADCs performing voltage-to-time-to-digital conversion. Conventional VTCs in TB ﬂash ADCs generate multiple time outputs or have nonlinear conversion gain, resulting in a large power consumption in time- to-digital converters (TDCs) due to power-inefﬁcient architec- tures using a lot of comparators. The proposed VTC generates a single time output with a large-and-linear conversion gain because the proposed