JSSC 2021第3期RF & Wireless28nmEqualizerPAM-4

A 60-Gbs PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization

一款采用2抽头直接判决反馈均衡的60Gbps PAM4有线接收器，具有低延迟和高能效特性。

28nm CMOS, 60 Gb/s, BER<1E-12, 1.1 pJ/b

PAM4接收器判决反馈均衡CMOS技术高速通信能效优化

▸创新点1：CMOS跟踪再生切片器设计，通过优化时钟到Q延迟和输出信号摆幅，显著提高了PAM4接收器的时序精度和信号完整性，支持60 Gb/s的高数据率传输。

▸创新点2：2抽头直接判决反馈均衡技术（DFE），利用切片器生成的轨到轨数字反馈信号，减少了延迟并放宽了夏季的稳定时间约束，从而在高数据率下实现了优异的误码率（BER <1E-12）。

▸创新点3：无需环路展开和电感带宽增强技术，通过创新的2抽头直接DFE和切片器设计，避免了传统方法中面积和功耗密集型的电路，实现了1.1 pJ/b的高能效。

▸创新点4：采用28纳米CMOS工艺实现的PAM4接收器，在8.2 dB损耗的信道下，仍能保持60 Gb/s的高速数据传输和极低的误码率，展示了其在高速有线通信中的实际应用潜力。

Abstract

This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating continuous time lin- ear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer (DFE) for applications in wireline communication. A CMOS track-and-regenerate slicer is proposed and employed in the PAM4 receiver. The proposed slicer is designed for the purposes of improving the clock-to-Q delay as well as the output signal swing. A direct DFE in a PAM4 receiver is made possible with the proposed s