JSSC 2021第3期Data Converters40nmSAR ADC

A 771-dB-SNDR 625-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Sh

提出增强型级间增益误差整形技术和一阶被动量化噪声整形技术，实现高性能ADC设计。

40nm CMOS, 100 MS/s, 77.1-dB SNDR, 6.25-MHz带宽, 1.38 mW功耗

级间增益误差整形数字误差反馈量化噪声整形模数转换器CMOS

▸增强型级间增益误差整形（GES）技术

▸数字误差反馈（DEF）方法

▸一阶被动量化噪声整形（NS）技术

Abstract

This article presents an enhanced interstage gain error shaping (GES) technique that adopts a digital error feed- back (DEF) method to address the truncation error in the prior implementation, which can extend the interstage gain error tolerance by ﬁve times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. This article also proposes a ﬁrst-order passive quanti- zation noise shaping (NS) technique that reduces the input-pair ratio of th