JSSC 2021第3期Data Converters45nm PDSOI CMOSDACPLL

A Fractional- N Reference Sampling PLL With Linear Sampler and CDAC Based Fracti

提出一种采用线性采样器和CDAC的分数-N参考采样锁相环，实现低噪声和高线性度。

7.7–9.1 GHz, 135 fs抖动(10 kHz–50 MHz), -55 dBc分数杂散, 4.5 mW功耗, FoM -250.8 dB

分数-N锁相环参考采样CDAC线性采样器量化误差消除

▸采用电容式数模转换器（CDAC）消除分数模式下的分频器量化误差

▸通过恒定放电电流实现参考采样相位检测器（RSPD）的线性化

▸使用单一电容阵列和多参考电压的高阶非线性消除方案

Abstract

In this article, a fractional- N reference sampling phase-locked loop (PLL) (RSPLL) is presented. A capacitor- based digital-to-analog converter (CDAC) is implemented at the output of the reference sampling phase detector (RSPD) to cancel the divider quantization error in fractional mode. The RSPD is linearized by maintaining a constant discharge current from the sampling capacitor. Although the discharging current source may induce some noise compared to a sampling PD. However, its noise can be