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JSSC 2021第3期Digital Circuits40nmNeural Network Accelerator

An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Condi

提出一种结合精度级联和零跳过的条件计算方案,用于高效DCNN加速器设计。
40nm CMOS, 0.6V, 24.97 TOPS/W, 0.0018 access/MAC
深度卷积神经网络硬件加速器条件计算精度级联零跳过
精度级联(PC)减少冗余卷积计算
零跳过(ZS)利用稀疏性减少时钟周期和内存访问
协同条件计算方案提升能效
Abstract
With its algorithmic success in many machine learning tasks and applications, deep convolutional neural net- works (DCNNs) have been implemented with custom hardware in a number of prior works. However, such works have not exploited conditional/approximate computing to the utmost toward elim- inating redundant computations of CNNs. This article presents a DCNN accelerator featuring a n ovel conditional computing scheme that synergistically combines precision cascading (PC) with zero skipping (ZS