← 返回 JSSC 论文列表JSSC 2021第3期Data Converters65nmDelta-Sigma ADCTime-Interleaved ADC
Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback
设计并实现了一款20MHz带宽的单比特连续时间ΔΣ ADC，采用65nm CMOS工艺，采样率2.56GHz。
65nm CMOS, 1.1V, 2.56GHz采样率, 82.1dB SNDR, 11.3mW功耗
连续时间ΔΣ调制器时间交织ADCFIR反馈DAC混合信号校准低功耗
▸2×时间交织ADC解决比较器亚稳态问题
▸4×时间交织虚拟地开关电阻FIR反馈DAC降低失真
▸混合信号校准解决DAC元件失配
Abstract
We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The mod- ulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2× time-interleaved ADC to address the problem of comparator metastability. A 4 × time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architec- ture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. T h ed e c i m a t o rd i s s i p a t e s1 3 . 5m W .