Low Bit-Depth ADCs for Multi-bit Quanta

Abstract

A 1024 × 896 test chip is presented in this article to explore a low-power readout circuit for a multi-bit quanta image sensor (QIS). Five well-known analog-to-digital converter (ADC) approaches [flash, pipeline, successive approximation register (SAR), cyclic, and single-slope (SS)] are studied, and two types of ADCs, namely, SAR ADCs and SS ADCs, are implemented in the sensor. The ADC power dissipations are compared under the condition of constant imaging throughput in counting photoelectrons. In QIS devices, one LSB corresponds to one photoelectron. Measurement results show that the power consumption of SAR ADC is better than that of the SS ADC and decreases by a factor of 17 when the resolution is changed from 1 b to 6 bits. By contrast, the power consumption of the SS ADCs decreases by a factor of 2.5. Thus, SAR ADCs seem more suitable for use in low-power multi-bit QIS.