A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single- Ended PAM-4 Transmitter With an Impedance- Matched Driver and Three-Point ZQ Calibration for Memory Interface Y

Abstract

A single-ended four-level pulse-amplitude modula- tion (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves PAM-4 linearity by allowing the driver to compen- sate for its impedance variation caused by the change in the drain–source voltage ( V DS) to suit the four output levels consid- ering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equal- ization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm 2 and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.