← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2021第4期Clocking & PLLs65nmVCO

A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation Jiannan Huang , Student Member , IEEE, and Patrick P . Mercier , Senior Member , IEEE

一种基于VCO的高动态范围传感器前端,采用差分脉冲编码调制和背景增益校准技术,实现超低失真和高性能。
65nm CMOS, 3.2µW, 89dB SNDR, 94dB DR, 500Hz带宽
VCO量化器差分脉冲编码调制背景校准动态范围传感器前端
采用差分脉冲编码调制(DPCM)降低VCO量化器输入信号幅度
背景数字增益校准克服VCO增益偏差
动态元件匹配(DEM)提升动态范围
Abstract
This article presents a high-dynamic-range (DR) voltage-controlled oscillator (VCO)-based front end for sensor readout applications. Unlike conventional VCO-based quantizers, which suffer from large voltage-to -frequency non-linearities, the proposed design leverages differential pulse-code modula- tion (DPCM) from compression theory to substantially reduce the amplitude of the signal incident to the VCO quantizer, thereby achieving an ultra-low total harmonic distortion (THD) of −112 dB. In addition, background digital gain calibration is employed to overcome gain deviation of the VCO, thus ensuring a robust design. Together with dynamic element matching (DEM), the techniques enable a high DR using only the first-order noise shaping inherent in VCO-based quantizers and a moderate 32 × oversampling ratio. Fabricated in 65 nm, the sensor front end consumes 3.2-µW power and achieves an SNDR of 89 dB and a DR of 94 dB in 500 Hz of bandwidth. Together with a 1.18- µV rms integrated input-referred noise, it achieves a noise efficiency factor (NEF) of 4 and a Schreier FoM of 171 dB.