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A 18-GbsPin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Perf
本文提出了一种1.2V、1.8Gb/s/pin的16Tb NAND闪存多芯片封装方案，采用第三代F-chip提升性能。
1.2V, 1.8Gb/s/pin, 16Tb
NAND闪存多芯片封装F-chipPCIe Gen4信号完整性
▸采用第三代F-chip提升数据吞吐量
▸双双向收发器架构和信号重定时方案
▸基于DLL的锁存技术提升信号完整性
Abstract
This article presents a 1.2-V , 1.8-Gb/s/pin 16-Tb
NAND flash memory multi-chip package incorporating 16 dies
of 1-Tb NAND flash memory and the third-generation F-chip.
The proposed third-generation F-chip is developed to meet the
performance requirements of a high-capacity storage device
that adopts a PCIe Gen four-host interface for higher data
throughput. It is implemented with dual bi-directional transceiver
architecture and signal retiming scheme to maximize the valid
data window opening on s