A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage Daehoon Na , Jang-woo Lee, Seon-Kyoo Lee, Hwasuk Cho, Junha Lee, Manjae Y ang, Eunjin Song, Anil Kavala, Tongsung Kim, Dong-Su Jang, Y oungmin Jo, Ji-Y eon Shin, Byung-Kwan Chun, Tae-sung Lee, Byunghoon Jeong, Chi-Weon Y oon, Dongku Kang, Seungjae Lee, Jungdon Ihm, Dae Seok Byeon, Jinyub Lee, and Jai

Abstract

This article presents a 1.2-V , 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional transceiver architecture and signal retiming scheme to maximize the valid data window opening on solid-state drive (SSD) channels. Also, it facilitates training between F-chip and NAND using an on-chip delay-locked loop whose locking is proposed in strobe-based NAND systems to achieve sufficient signal integrity (SI) of the in-package channel at a speed of 1.8 Gb/s/pin. Embedded built-in self-test evaluates un-selected pa ths and determines if re-training is required without losing data throughput performance. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.