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A Proactive System for V oltage-Droop Mitigation in a 7-nm Hexagon TM Processor
7纳米Hexagon处理器中主动时钟门控系统通过电压跌落缓解提升性能或能效
10%更高的时钟频率或5%更低的供电电压
电压跌落时钟门控数字信号处理器电源配送网络能效优化
▸主动时钟门控系统（PCGS）
▸数字功率计（DPM）监测每周期功耗
▸电压-时钟门控（VCG）电路与电源配送网络（PDN）模型预测电压响应
Abstract
A proactive clock-gating system (PCGS) in a 7-nm
Qualcomm® HexagonTM digital signal processor (DSP) improves
performance or energy efficiency by reducing the magnitude
of supply voltage ( V
DD) droops. The PCGS integrates a digital
power meter (DPM) to monitor the power per cycle based
on microarchitectural events and a voltage-clock-gating (VCG)
circuit with a power-delivery-network (PDN) model to predict
the V
DD response to DPM power changes. When the PDN model
anticipates a potential VDD-droo