← 返回 JSSC 论文列表JSSC 2021第4期Analog Circuits0.18μm CMOSBandgap Reference
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3 σ Inaccuracy of +0.02%, − 0.12% for Battery-Monitoring Applications Jun-Ho Boo , Student Member , IEEE
提出一种单修调开关电容带隙基准电路,采用β补偿和曲率校正技术,结合DEM技术,实现高精度温度稳定性。
3σ不准确度+0.02%, −0.12%(-40°C至125°C),功耗17μA@27°C,面积0.38mm²
带隙基准开关电容单修调β补偿动态元件匹配
▸创新点1:单修调技术(系统创新) - 通过单次室温修调实现全温度范围内的PTAT误差消除,显著简化了传统多温度点修调的复杂流程,同时达到±0.12%的3σ精度指标。
▸创新点2:β补偿与曲率校正(电路创新) - 采用β补偿技术抵消PNP晶体管电流增益的非线性影响,结合高阶曲率校正电路,将非PTAT误差降低至0.02%量级。
▸创新点3:动态元件匹配技术(方法创新) - 创新性地利用ΔΣ ADC的抽取滤波器实现数字域低通滤波DEM,有效抑制偏置电流、β失配及SC求和放大器增益系数的失配误差。
▸创新点4:开关电容架构创新(电路创新) - 采用SC电路实现带隙基准求和放大,相比传统电阻方案,在0.18μm CMOS工艺下实现0.38mm²的小面积和17μA的低功耗。
Abstract
This article presents a single-trim switched capaci- tor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, β-compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In con- junction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( β), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a β of about 2.7 at 27 ◦C in a 0.18- μmC M O S process. The proposed SC BGR achieves a 3 σ inaccuracy of +0.02%, −0.12% from −40 ◦C to 125 ◦C. From a 1.8-V supply voltage, it consumes 17 μAa t2 7 ◦C and occupies an active area of 0.38 mm 2.