A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Abstract

A side-channel attack (SCA) hardened AES-128 and RSA crypto-processor in 14-nm CMOS with measured resistance to correlation power/electromagnetic analysis (CPA/CEMA) in both time and frequency domains is demonstrated. While pre- viously reported linear low-dropout regulators (LDOs) offer improvements in minimum-time-to -disclose (MTD) of extracted key bytes in the time domain, their transformations are less effective against frequency-domain attacks. This article describes a non-linear digital LDO (NL-DLDO) with control loop random- izations that bolster SCA resistance in the frequency domain. The NL-DLDO cascaded with an AES engine augmented with arith- metic countermeasures enables >250K× improvement in MTD, with no CPA/CEMA/DNN attacks detected after 1-B encryptions, with 8% power and 10% area overheads incurred by arithmetic techniques. The RSA-4K crypto-processor implements exponent magnitude and timing randomizations along with dynamic mem- ory addressing to mitigate time- and frequency-domain attacks. The countermeasures enable 711 × suppression in means separa- tion in current/EM magnitudes from 3.1 mV to 4.35 µV , reducing attacker’s accuracy to an ineffect ive random guess classification, while limiting area and performance overheads to <0.05% and 3.25%, respectively.