Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Abstract

The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has become new technology platform to overcome the issue in power consumption of logic for the application from IoT to AI; however, STT-MRAM has a tradeoff relationship between endurance, retention, and access time. This is because the MTJ device used in STT-MRAM is a two-terminal device, and excessive read current for high-speed readout can cause unexpected data writing, or so-called read disturbance. In order to meet the demand for the realization of high-speed nonvolatile memory, the development of new memories based on innovative circuit, device, and integration process is required. In this article, we demonstrate an SOT-MRAM, a nonvolatile memory using MTJ devices with spin-orb it-torque (SOT) switching that have a read-disturbance-free characteristic. The SOT-MRAM fabricated using a 55-nm CMOS process is implemented in a dual-port configuration utilizing a three-terminal structure of the device for realizing a wide bandwidth applicable to high-speed applications. In addition, a read-energy reduction technique called a self-termination scheme is also implemented. Through the measurement results of the fabricated prototype chip, we will demonstrate the proposed SOT-MRAM achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under a magnetic-field-free condition.