← 返回 JSSC 论文列表JSSC 2021第6期Other0.18-μmBandgap Reference
A1 . 8 - n W ,− 73.5-dB PSRR, 0.2-ms Startup Time, CMOS V oltage Reference With Self- Biased Feedback and Capacitively Coupled Schemes Cheng-Ze Shao , Student Member , IEEE
本文提出了一种采用自偏置和电容耦合方案的纳瓦级CMOS电压基准，显著提升了PSRR和建立时间。
0.18-μm CMOS, 1.8 nW, 0.2 ms建立时间, -73.5-dB PSRR
CMOS电压基准自偏置电容耦合PSRR纳瓦级功耗
▸创新点1：自偏置方案（方法创新） - 采用自偏置技术替代传统偏置电路，显著降低功耗至1.8 nW，同时实现-73.5 dB的PSRR，解决了低功耗与高PSRR的矛盾。
▸创新点2：电容耦合方案（电路创新） - 通过电容耦合技术优化信号路径，将启动时间缩短至0.2 ms，相比传统方案提升了一个数量级，且无需额外功耗。
▸创新点3：无辅助放大器设计（系统创新） - 完全摒弃功耗密集型辅助放大器和偏置电路，通过自洽架构实现62 ppm/°C的温度系数，在-40°C至130°C范围内保持稳定性。
▸创新点4：全集成CMOS实现（工艺创新） - 在0.18μm CMOS工艺中集成所有功能模块，实现1.1 mV的标准偏差和0.43%的3σ精度，验证了方案的工艺兼容性。
Abstract
This article presents a nanowatt CMOS voltage reference using self-biased and capacitively coupled schemes for improving the power supply rejection ratio (PSRR) and settling time without power-intensive auxiliary amplifiers and bias circuits. The chip was fabricated in a 0.18- μm CMOS process. With the proposed schemes, the design can achieve a 1% settling time of 0.2 ms and a −73.5-dB PSRR at 100 Hz while only consuming 1.8 nW. The average temperature coefficient of 15 chips is 62 ppm/ ◦C in a temperature range from −40 ◦C to 130 ◦C. The average voltage at 20 ◦C is 0.26 V , while the standard deviation is 1.1 mV and 3 σ accuracy is 0.43%.