A 0.25–0.4-V , Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic

Abstract

This article presents an ultra-low-voltage phase- locked loop (ULVPLL) with the minimum supply voltage at 0.25 V . The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Imple- mented in 40-nm CMOS with core area of 0.00873 mm 2, the 0.15–1.6-GHz ULVPLL is capable of operation under a 0.25–0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is −58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V s upply) and −48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).