JSSC 2021第6期Power Management40nmCharge PumpPLL

19 A 02504-V Sub-011-mWGHz 01516-GHz PLL Using an Offset Dual-Path Architecture

提出一种0.25V超低电压锁相环，采用偏移双路径架构降低电荷泵设计难度

0.15-1.6GHz工作频率，0.25-0.4V供电，0.106mW/GHz能效(1.6GHz@0.4V)

超低电压锁相环双路径架构动态电荷泵40nm CMOS能效优化

▸偏移双路径环路架构消除电荷泵电流匹配需求

▸动态电荷泵去除电流源/镜和运放，降低工作电压至0.3V以下

▸在40nm工艺下实现0.00873mm²核心面积

Abstract

This article presents an ultra-low-voltage phase- locked loop (ULVPLL) with the minimum supply voltage at 0.25 V . The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This signiﬁcantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence