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20 A 134-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Rec
采用28nm CMOS工艺设计的1.3–4GHz数字延迟锁定环，通过顺序延迟控制和可重构延迟线降低抖动和锁定时间。
28nm CMOS, 1.3–4GHz, 6.5mW, 12.5ps峰峰值抖动
数字延迟锁定环顺序延迟控制可重构延迟线偏斜校准低抖动
▸创新点1：顺序延迟控制技术（方法创新）通过顺序更新延迟码而非传统并行方式，显著降低bang-bang抖动至传统DDLL的1/3，峰值抖动从15.6 ps改善至12.5 ps，同时降低锁定时间。
▸创新点2：可重构延迟线设计（电路创新）采用三模式可调最小延迟差结构，动态调整正交时钟的最小延迟差，实现1.3-4 GHz超宽频率范围工作，突破传统固定延迟线限制。
▸创新点3：共享子块的偏斜校准电路（系统创新）利用顺序延迟控制的现有子模块实现工艺偏差补偿，硬件成本降低30%以上，以正交时钟平均相位差作为90°基准进行高精度校正。
▸创新点4：基于正交时钟正沿采样的新型占空比校正器（DCC）（电路创新）通过收集正交相位时钟正边缘实现50%占空比校准，无需额外延迟链，功耗仅增加0.2 mW。
Abstract
A 1.3–4-GHz quadrature-phase digital delay-locked
loop (DDLL) with sequential delay control and a reconfigurable
delay line is designed using a 28 nm CMOS process. The time
resolution of the DDLL is reduced by updating the delay code
sequentially. A bidirectional shift register enables this operation
with low power, resulting in bang-bang jitter that is three
times smaller than that of a conventional DDLL. Conventional
delay control is replaced with sequential delay control after a
DDLL lock to r