← 返回 JSSC 论文列表JSSC 2021第6期RF & Wireless0.18μm
A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D
一款用于微型3D超声系统的36通道自校准前端ASIC,集成发射、接收和ADC功能,功耗低且支持校准。
0.18μm CMOS, 13.2-Vpp脉冲, 1.14-mW/通道平均功耗
ASICpMUT自校准电荷回收动态位共享
▸电荷回收高压发射器(CRHV-TX)减少42.2%峰值功耗
▸动态位共享ADC(DBS-ADC)共享相邻通道的最高有效位
▸模拟前端(AFE)实时自适应增益调整
Abstract
We present an area- and power-efficient application- specific integrated circuit (ASIC) for a miniaturized 3-D ultra- sound system. The ASIC is designed to transmit pulse and receive echo through a 36-channel 2-D piezoelectric Micromachined Ultrasound Transducer (pMUT) array. The 36-channel ASIC integrates a transmitter (TX), a receiver (RX), and an analog-to- digital converter (ADC) within the 250- μm pitch channel while consuming low-power and supporting calibration to compensate for the process variation of the pMUT. The charge-recycling high-voltage TX (CRHV-TX) in standard CMOS generates up to 13.2-V PP pulse while reducing 42.2% peak TX power con- sumption. Also, each CRHV-TX automatically calibrates exci- tation voltage according to acoustic pressure of pMUT. The dynamic-bit-shared ADC (DBS-ADC) shares the most significant bits (MSBs) among four channels based on the signal similarity between adjacent channels. The analog front end (AFE) with a received signal sensitivity indicator (RSSI) changes its gain adaptively in real time depending on input signal strength. The ASIC consumes 1.14-mW/channel average power with 1-kHz pulse repetition frequency (PRF) and three TX pulses per cycle. The ASIC in 0.18- μm 1P6M Standard CMOS has been verified with both electrical and acoustic experiments with a 6 ×6p M U T array. Manuscript received June 8, 2020; revised September 14, 2020 and November 17, 2020; accepted December 21, 2020. Date of publication January 29, 2021; date of curre