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A Time-Based Intra-Memory Computing Graph Processor Featuring A Wavefront Expan
开发了一种基于时间的65nm混合信号集成电路，用于解决最短路径问题。
559 million traversed edges per second, 105× improved energy efficiency, 1.79 ns per node, 26.4 mW peak power
时间计算内存内计算最短路径A*算法波前扩展
▸内存内计算：将数字电路与内存集成在同一芯片中，减少数据传输延迟，显著提升计算效率，实现559百万边/秒的遍历速度。
▸波前扩展技术：采用异步波前扩展机制，通过前导脉冲从起始节点传播并异步锁存到邻近顶点单元，实现高效的路径搜索。
▸A*算法启发式距离梯度：在核心外围引入梯度机制，结合A*算法的预测距离启发式，优化路径规划精度和计算速度。
▸混合信号设计：采用65nm混合信号专用集成电路，结合模拟与数字信号处理，降低功耗至26.4mW，提升能源效率105倍。
Abstract
A mixed-signal, time-based 65-nm application-
specific integrated circuit is developed for solving shortest-path
problems. Digital circuits are collocated with the memory as
intra-memory computing. The core follows similar principles
from wave routing and, additionally, incorporates a gradient
on the periphery of the core to implement the A ∗ algorithm
predicted distance heuristic. A leading pulse is propagated from
start nodes and is asynchronously latched in neighboring vertex
cells and pushed