← 返回 JSSC 论文列表JSSC 2021第7期MemorySRAMNeural Network Accelerator
Colonnade A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro
Colonnade提出了一种全数字位串行计算内存宏，支持1-16位可配置输入和权重精度。
无
数字计算内存位串行计算可配置精度神经网络加速MAC操作
▸全数字电路实现，避免工艺变异和噪声影响
▸支持1-16位输入和权重精度的完全可配置
▸采用自定义XNOR门和全加器实现位级MAC操作
Abstract
This article (Colonnade) presents a fully digital
bit-serial compute-in-memory (CIM) macro. The digital CIM
macro is designed for processing neural networks with recon-
figurable 1–16 bit i nput and weight precisions based on bit-
serial computing architecture and a novel all-digital bitcell
structure. A column of bitcells forms a column MAC and used
for computing a multiply-and-accumulate (MAC) operation. The
column MACs placed in a row work as a single neuron and
computes a dot-product, which i