← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2021第7期Digital Circuits40nm

PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key

提出一种新型PUF架构,通过运行时自适应纠错降低能耗并提升可靠性
1.27 pJ/bit (40nm CMOS), 1.8X能效提升
物理不可克隆函数运行时自适应错误校正码密钥生成能效优化
运行时不稳定监测与自适应纠错
轻量级机器学习算法动态调整纠错位数
可调ECC实现能耗与安全性的灵活权衡
Abstract
This paper presents a novel PUF-based key generation architecture featuring run-time instability monitoring and adaptive error correction, overcoming the limitations of conventional architectures with fixed correction bits set at design or testing time. Run-time information from on-chip sensors is fused by a lightweight machine learning algorithm evaluating the minimum number of correction bits necessary to meet the required key error rate (KER). The number of correction bits in the subsequent er