PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via

Abstract

This paper presents a novel PUF-based key generation architecture featuring run-time instability monitoring and adaptive error correction, overcoming the limitations of conventional architectures with fixed correction bits set at design or testing time. Run-time information from on-chip sensors is fused by a lightweight machine learning algorithm evaluating the minimum number of correction bits necessary to meet the required key error rate (KER). The number of correction bits in the subsequent error-correcting code (ECC) is made tunable and adapted accordingly. This reduces the dominant ECC energy compared to traditional correction bits margining for the worst case across corners, operating conditions, and application-specific KER target. The proposed architecture is demonstrated and exemplified by a 40-nm testchip implementing a monostable PUF, the proposed instability sensors, and BCH ECC featuring scalable correction. 1.8X energy reduction was measured over a baseline margined for iso-KER. Its 1.27 pJ/bit energy is the lowest com- pared to prior art that includes the necessary ECC. Adjustable correction also enables application-level energy-security tradeoff, saving energy when the KER target can be relaxed. On-chip monitoring reduces the traditionally high cost of PUF testing due to the necessary voltage/temperature sweeps.