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A2 × Time-Interleaved 28-GS/s 8-Bit 0.03-mm 2 Switched-Capacitor DAC in 16-nm FinFET CMOS
一种紧凑型2倍时间交织开关电容DAC，适用于数字密集型发射机架构。
28-GS/s, 8-bit, 0.03 mm², 0.8-V, 88 mW
时间交织开关电容DACFinFET电荷重分配数字发射机
▸创新点1：采用逆变器和亚飞法拉级开关电容（电路创新）。该设计摒弃传统电流导向架构，利用FinFET技术优势，通过逆变器和超小电容（sub-femtofarad）实现高密度集成，面积仅0.03 mm²，显著降低芯片面积。
▸创新点2：基于并行电荷重分配架构（系统创新）。通过并行电荷分配机制提升转换速度至28 GS/s，同时支持8位分辨率，在首奈奎斯特区实现SFDR≥37 dB和IM3≤-45.6 dBc的高线性度性能。
▸创新点3：分离电平生成、脉冲定时和输出功率生成（架构创新）。模块化设计将关键功能解耦，优化时序控制精度（0.8V单电源供电）与输出摆幅（0.32Vpp差分），功耗控制在88 mW。
▸创新点4：2×时间交织技术（时序创新）。通过双通道交织采样提升有效采样率，同时利用16nm FinFET工艺特性降低时钟偏差影响，确保高频信号完整性。
Abstract
This article presents a compact 2× time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementa- tion departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC’s architecture is based on parallel charge redistribution and sepa- rates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm 2 in 16-nm CMOS and supports up to 0.32-V pp signal swing across its differential 100- /Omega1load. It achieves an SFDR ≥37 dB and an IM3 ≤− 45.6 dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.