A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS

Abstract

We demonstrate a four-to-one 100-GS/s time inter- leaver realized in a 55-nm BiCMOS technology. The inter- leaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero genera- tion and summing architecture. This sub-interleaver architec- ture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) mea- surements have been performed revealing the interleaver’s ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM- 4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.