A 51-pJ/Pixel 33.7-dB PSNR 4 × Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing Chanmin Park , Student Member , IEEE, Wenda Zhao , Student Member , IEEE, Injun Park , Student Member , IEEE

Abstract

This article presents a CMOS image sensor (CIS) with column-parallel single-sh ot compressive sensing (CS) for always-on Internet-of-Things (IoT) application, which achieves an energy efficiency of 51 pJ/pixel, while maintaining high image quality of PSNR > 33.7 dB and SSIM > 0.89. This is enabled by an energy-efficient encoder, which replaces a densely populated CS encoding matrix with a highly sparse pseudo-diagonal one. Since the proposed column-parallel CS encoder can be implemented directly at pixel outputs with an energy-efficient switched-capacitor matrix multiplier, data compression is achieved prior to the pixel digitization, thereby greatly reducing ADC power, data size, and I/O power. The energy efficiency of the image sensor is further improved by using dynamic single-slope ADCs. A prototype VGA image sensor implemented in a 110-nm CMOS process consumes only 0.7 mW at 45 frames/s. The corresponding energy per pixel (51 pJ/pixel) amounts to more than 5 × improvement over the previous low-energy benchmark for CS image sensors.