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A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge
65纳米工艺下采用自适应匹配线放电方案的低功耗高性能TCAM设计
65nm CMOS, 1.1V, 100MHz, 0.6fJ/bit/search
TCAM低功耗自适应匹配线时序校准能效优化
▸创新点1：自适应匹配线放电方案（电路创新） - 通过动态控制匹配线放电路径，消除不必要的放电操作和冗余搜索线切换，在1.1V/100MHz下实现搜索延迟降低69%和搜索能耗节省37%。
▸创新点2：转置单元拓扑结构（电路创新） - 采用新型单元布局方式实现选择性匹配线下拉路径控制，同时缩小阵列面积，提升集成密度以适应65nm工艺节点需求。
▸创新点3：时序校准技术（系统创新） - 通过动态调整匹配线电压摆幅的时序，在宽电压范围内（测量数据包含1.1V工况）实现最优功耗-性能平衡，使能效达到0.6fJ/bit/search。
▸创新点4：匹配线升压技术（电路创新） - 创新性地引入ML电压提升机制，与自适应放电方案协同工作，进一步降低比较操作时的动态功耗，贡献8%的能效FoM提升。
Abstract
This article presents an adaptive match-line (ML) discharge scheme for low-power, high-performance, and com- pact ternary content addressable memory (TCAM). In the proposed TCAM, the transposed cell topology enables the selec- tively controlled ML pull-down path and compact array area. By employing the adaptive ML discharge and ML boosting scheme, unnecessary ML discharge and redundant search-line (SL) switching are eliminated for low-cost TCAM search opera- tion. In order to minimize ML voltage swing at a wide voltage range, a timing calibration scheme is also adopted in the proposed TCAM. A 128 × 64 test chip implemented with 65-nm CMOS technology shows that the proposed adaptive ML discharge improves up to 69% of search delay and saves 37% of search energy compared with the conventional approach at 1.1 V , 100 MHz. The measurement result shows energy efficiency of 0.6 fJ/bit/search and 8% improvement of figure-of-merit (FoM) (energy/bit/search) compared with the state-of-the-art works.