JSSC 2021第8期Memory28nmSRAM

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Co

提出级联电流镜电路，提升SRAM内存计算线性度和一致性。

28nm CMOS, 0.8V, 0.9V

SRAM内存计算级联电流镜线性度一致性

▸创新点1：级联电流镜电路（电路创新）- 通过引入级联电流镜（CCM）电路，显著改善了SRAM存内计算的线性度和一致性，减少了整数非线性误差高达70%，并提高了计算一致性56.84%。

▸创新点2：双字线6T SRAM单元（电路创新）- 采用双字线设计的6T SRAM单元，结合CCM电路，进一步降低了延迟，提升了计算一致性，优化了多行读取操作的性能。

▸创新点3：电压钳位和电流比例镜像（电路创新）- 在每个位线上仅增加四个晶体管，实现了电压钳位和电流比例镜像功能，有效解决了多行读取导致的非线性问题，提升了电路稳定性。

▸创新点4：系统级验证与应用（系统创新）- 通过在卷积神经网络分类任务中验证，MNIST数据集准确率达到91%，CIFAR-10数据集准确率达到86%，证明了该技术在AI应用中的实际性能提升。

Abstract

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlin- earity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T