Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

Abstract

Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlin- earity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T SRAM cell with double word lines operating with the CCM further reduced the delay and improved the computational consistency. We applied the structure to numerous prior studies and evaluated them using the 28-nm complementary metal– oxide semiconductor process. The measurement results show that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8-V supply, and the computational consistency is substantially improved by 56.84% at 0.9-V supply. In addition, we verified the performance improvement through classification using a convolutional neural network, achieving 91% accuracy in the MNIST and 86% accuracy in the CIFAR-10. The area overhead was 1.77% in a 512 × 512 SRAM array when integrating the proposed CCM circuit.