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JSSC 2021第10期Data Converters28nmDAC

A 10-GS/s NRZ /Mixing DAC With Switching-Glitch Compensation Achieving SFDR > 64/50 dBc Over the First /Second

提出一种带开关毛刺补偿的10GS/s NRZ混合DAC,显著提升线性度。
14-bit 10-GS/s, SFDR >64 dBc(第一奈奎斯特区), >50 dBc(第二奈奎斯特区)
数模转换器开关毛刺补偿高线性度奈奎斯特区动态范围
创新点1:开关毛刺补偿技术(SGC)是一种电路创新,通过生成与主DAC开关毛刺互补的毛刺信号,显著降低了代码依赖性毛刺效应,使输出毛刺量变为代码无关,从而将SFDR提升高达20 dB。
创新点2:毛刺复制器作为方法创新,精确复制主DAC的开关毛刺并生成互补信号,通过动态匹配技术确保补偿精度,在28nm CMOS中实现了14位10-GS/s的高线性度输出。
创新点3:解相关器作为系统创新,通过随机化毛刺复制器的失配效应,有效消除了输出频谱中的失配诱导杂散,使得DAC在第二奈奎斯特区仍保持>50 dBc的SFDR性能。
创新点4:混合架构设计(NRZ/Mixing DAC)结合SGC技术,在10 GHz输出频率下实现12.5 dB的SFDR优势,同时将支持50 dBc SFDR的最高输出频率提升1.4倍,属系统级创新。
Abstract
This article presents a high-linearity wide- bandwidth current-steering digital-to-analog converter (DAC). To overcome the code-dependent current-switching glitch effect, which seriously degrades the DAC linearity, a switching-glitch compensation (SGC) technique, which is realized with glitch duplicators, is proposed to generate a complementary amount of switching glitch at the DAC output. Hence, the amount of switching glitch at the DAC output becomes code-independent, thus improving the linearity of the DAC output. In addition, a decorrelator is proposed to randomize the mismatch effect of the glitch duplicators, thus eliminating the mismatch-induced spur at the DAC output spectrum. A 14-bit 10-GS/s non-return-to-zero (NRZ)/Mixing DAC with SGC is realized in 28-nm CMOS. Measurement results show that the spurious free-dynamic range (SFDR) is improved up to around 20 dB by the SGC. Therefore, this DAC with SGC achieves an SFDR > 64 dBc over the entire first Nyquist zone and >50 dBc over the entire second Nyquist zone. Compared to prior state-of-the-art CMOS DACs with an output frequency ( f out ) ≥ 3.4 GHz, this DAC with SGC achieves a 12.5-dB better SFDR with fout near 10 GHz and a 1.4x higher fout with an SFDR larger than 50 dBc.