An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundan

Abstract

A redundancy eliminated flip-flop (REFF) is proposed targeting wide-range v oltage scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low-power (LP) and reliable operation even in the sub-threshold voltage regime. First, redundant internal clock transitions are eliminated without degrading reliability by finding the optimal way of generating internally inverted clock to reduce dynamic power consumption. Then redundant transistors are identified and eliminated with