Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc

Abstract

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversam- pling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm 2 area.