JSSC 2021第11期mm-Wave65nm

A 200-GHz Power Ampliﬁer With a Wideband Balanced Slot Power Combiner and 9.4-dBm Psat in 65-nm CMOS: Embedded Power Ampliﬁcation

研究高频毫米波功率放大器的增益与嵌入放大单元对输出功率的影响，提出匹配级联单元和差分槽功率合成器，实现200 GHz高功率输出。

65nm CMOS, 2.4V, 732mW, PAE 1.03%, Psat 9.4 dBm, OP1dB 6.3 dBm, 最大增益 19.5 dB

功率放大器毫米波匹配级联功率合成器高频

▸创新点1：匹配级联单元设计（电路创新） - 提出了一种新型高频高功率放大单元（matched cascode），通过优化级联结构和阻抗匹配，显著提升了在200 GHz频段的功率增益和输出功率，实现了19.5 dB的最大功率增益。

▸创新点2：差分槽功率合成器（系统创新） - 设计了一种宽带平衡槽功率合成器（SPC），通过分析其等效电路并优化布局，有效降低了匹配损耗，将输出功率提升至9.4 dBm（饱和功率）和6.3 dBm（1dB压缩点）。

▸创新点3：增益与输出功率优化（方法创新） - 通过推导嵌入式放大单元的功率方程并绘制功率等高线，提出了一种基于增益平面的最优嵌入设计方法，在给定增益目标下最大化输出功率，理论指导性强。

▸创新点4：高效率实现（电路创新） - 在65nm CMOS工艺下实现2×8 PA阵列，通过电源电压（2.4V）和偏置优化，在732 mW功耗下达到1.03%的功率附加效率（PAE），兼顾高频与能效。

Abstract

The effect of gain and embedding of amplifying cells (amp-cell) on the output power of power ampliﬁers (PAs) at high mm-wave frequencies is studied. This is the frequency range where matching loss becomes comparable with the gain of the amp-cell in most silicon technologies. By deriving power equations of embedded amp-cell, power contours are plotted in the gain plane and an optimum embedding is designed to maximize the output power for a desired gain. To showcase the theory, a high-frequency, high-power amp-cell, called matched cascode, is introduced and subsequently embedded to boost both power gain and output power. To increase the output power even further, a differential slot power combiner (SPC) is introduced and its equivalent circuit is analyzed. Finally, using the embedded matched cascode cell, and the SPC, a 2 × 8 PA is implemented in 65-nm bulk CMOS. It consumes 732 mW from 2.4-V supply voltage, with a maximum power-added efﬁciency (PAE) of 1.03%. The PA features a P sat and OP1dB of 9.4 and 6.3 dBm, respectively, at 200 GHz, and a maximum power gain of 19.5 dB.